1. Field of the Invention
This invention relates generally to the field of semiconductor device fabrication and more specifically to the fabrication of a semiconductor device having a recessed gate.
2. Background of the Invention
As integrated circuit technology advances and integrated circuit device dimensions decreases, it has become increasingly common to employ trench isolation methods to form trench isolation regions between active regions of a semiconductor device. Such trench isolation methods may employ chemical mechanical polishing (CMP) to provide a nominally planarized surface for an isolation trench that has been filled with an insulator. Typically, a CMP planarization of a wafer involves holding the wafer against a rotating polishing pad that is subjected to a silica-based alkaline slurry. The polishing pad also applies pressure against the wafer.
While it is desirable to use CMP planarization during the fabrication of semiconductor devices, the CMP planarization step may present some problems and drawbacks. For example, each additional CMP step leads to additional costs and additional processing time in the semiconductor fabrication process.
Additionally, a CMP step on a newly formed layer on the wafer may cause alignment targets thereon to lose their steps after the CMP method is performed. The CMP planarization step may also lead to "over polishing" (i.e., removal of material that was not intended to be removed). All of the above results may contribute to defective devices, loss of device yield, and lack of device reliability.
In prior art semiconductor devices having the elevated source/drain configuration, a CMP step is typically required to planarize the isolation regions. Furthermore, an additional CMP step (i.e., a pre-contact CMP step) is required to planarize the surfaces of the gates in these prior art devices before forming the contacts on the gate and source/drain region surfaces. This additional CMP step can lead to the problems mentioned above.
Thus, there is a need for a semiconductor device that can be fabricated with a reduction in the number of CMP planarization steps. What is further needed is a method of fabricating a semiconductor device with a reduction in the number of CMP planarization steps in the fabrication process.